1. Field of the Invention
The present invention relates generally to Input/Output interconnects. More particularly, the present invention relates to supporting global input/output interconnect features on ports of a midpoint device.
2. Description of the Related Art
In end-to-end network, sessions are negotiated and packets encoded/decoded at end points in the network. Thus, if a first device encodes a packet according to an agreed-upon protocol and then sends the packet to a second device that shares the protocol, the second device will decode the packet.
A common data protection feature of end-to-end networks is an end-to-end cyclical redundancy check (ECRC). This involves the embedding of a code, known as the CRC code, in a packet. This CRC code may be, for example, a calculated short, fixed-length binary sequence for each block of data. The code is then sent along with the block when the block is transmitted to another device. When the block is read or received the end point device repeats the calculation. If the new calculated CRC does not match (or in some cases, cancel out) the earlier calculated code, then the block contains a data error and the end point device may take corrective action such as rereading or requesting the block be sent again.
On major source of CRC errors is alpha (α) particle contamination that may be existent or occur when data is written to memory. Alpha particles can cause what is termed a ‘soft error’, which is a change of charge on a line that may cause the incorrect state to be saved. Most commonly these affect Static Random Access Memories (SRAMs) due to their high density of storage states, although any stateful logic can be affected. Consequently, a proper CRC check has become a necessary aspect of data communications.
There are many different computer I/O interconnect standards available. One of the most popular over the years has been the peripheral component interconnect (PCI) standard. PCI allows a bus to act like a bridge, which isolates a local processor bus from the peripherals, allowing a Central Processing Unit (CPU) of the computer to run must faster.
Recently, a successor to PCI has been popularized. Termed PCI Express (or, simply, PCIe), PCIe provides higher performance, increased flexibility and scalability for next-generation systems, while maintaining software compatibility with existing PCI applications. Compared to legacy PCI, the PCI Express protocol is considerably more complex, with three layers—the transaction, data link and physical layers.
In a PCI Express system, a root complex device connects the processor and memory subsystem to the PCI Express midpoint device fabric comprised of zero or more midpoint device devices. In PCI Express, a point-to-point architecture is used. Similar to a host bridge in a PCI system, the root complex generates transaction requests on behalf of the processor, which is interconnected through a local I/O interconnect. Root complex functionality may be implemented as a discrete device, or may be integrated with the processor. A root complex may contain more than one PCI Express port and multiple midpoint device devices can be connected to ports on the root complex or cascaded.
A PCIe midpoint device can be used to operate the PCIe intercommunication standard. The midpoint device contains multiple ports that each connect to a different device. As described previously, ECRC is desired to be implemented in PCIe. However, not all devices support ECRC. Because ECRC requires an end-to-end connection, if a receiving device does not support ECRC than any communications to the device, even if sent by devices that do support ECRC, do not utilize ECRC and thus are at risk for the data protection issues mentioned earlier.
Referring to FIG. 1, a PCIe midpoint device 100 may have multiple ports 102a-102h. If device 104 supports ECRC and device 106 also supports ECRC, then communication 106 between devices 104 and 106 through PCIe midpoint device 100 is performed using ECRC. However, if device 110 does not support ECRC, then communication 112 between devices 104 and 108 through PCIe midpoint device 100 is not performed using ECRC for any portion of that path.
A similar problem occurs with maximum payload sizes of packets. Referring to FIG. 2, typically, a maximum payload size is set and all devices connected to PCIe midpoint device 200 must abide by the maximum payload size, even if individual devices support a higher payload size. Thus, if the maximum payload size in the system is 128 bytes, due to device 202 only supporting a maximum payload size of 128 bytes, while device 204 supports a maximum payload size of 512 bytes and device 206 supports a maximum payload size of 256 bytes, then a communication 208 between device 204 and device 206 will have a maximum payload size of 128 bytes, requiring more packets in order to send the same payload. There is a typical overhead of about 20-28 bytes per payload, thus the larger the payloads the more efficient the system runs.
Additionally, the system-wide payload size is typically set at the lowest payload size of any of the devices connected to the midpoint device 200. This, however, creates an unfortunate situation where a single device with a lower maximum payload size, such as an inexpensive endpoint added to an enterprise class system, will reduce the capability of the rest of the system. Indeed, a system thoroughly tested for performance may meet benchmarks, only to have system performance degrade when someone adds in a new endpoint in the field.